Pushpalatha Pondreti

Mrs.Pushpalatha Pondreti

assistant professor
Department:Electronics and Communication Engineering
Qualification:M.Tech, (Ph.D)
Phone(Office):9705510601
Mobile:9705510601
Email:pushpalatha86@gmail.com
Date of Birth:09/08/1986
Date of Joining:02/01/2013
Subjects Taught:VLSI Design, Pulse and Digital Circuits, Digital System Design & Digital IC Applications, Digital Logic Design, Digital System Design, DSP Processors and Architectures, Embedded Systems, Advanced Digital Signal Processing, Digital IC Applications, VLSI Signal Processing, Internet of Things, Memory Architectures
Research Area:VLSI Design
Teaching Experience:11 years
Research Experience:7 years
Industry/Professional Experience:Nil
Personal Webpage :
Google Scholar link:
Staff Image

[1] P.Sowjanya, P.Pushpalatha, “transposed form fir filter Implementation Using Reconfigurable Architectures”, International journal of engineering research and technology(IJERT, volume 2, Issue 8(Auguest-2013).
[2] Sekhar, P.Pushpalatha, “Low power design of Johnson counter using DDFF featuring efficient embedded logic and clock gating”, International journal of engineering research and general science (IJERGS, volume 2, Issue 5(2014). Impact factor--- 3.843
[3] Shaik kouser rashmi, P.Pushpalatha, “Low power area efficient parallel FIR implementation using fast FIR algorithmic strength reduction technique with carry skip adder”, International journal of scientific engineering and technology research(IJSETR, volume 4, Issue 35(2015 AUGUST). Impact factor--- 3.462
[4] P.Bala kishore, Mrs. P. Pushpa latha “An FPGA Implementation of Faster Compression of the Partial Product Array in Two’s Complement Multiplier” International Journal of Advanced and Innovative Research (2278-7844) / # 217 / Volume 2 Issue 9, September 2013.
[5] B Prasanthi , P.Pushpalatha “Design of Low-Voltage and low-Power inverter based Double Tail Comparator” International Journal of Engineering Research and General Science Volume 2, Issue 5, August-September, 2014 ISSN 2091-2730.
[6] G.DEVI SUDHARANI , P. PUSHPALATHA , M.RAMKUMAR, “ARCHITECTURE OF PREFIX ADDER FOR IMPLEMENTATION OF FIR FILTER AND VERIFICATION USING UVM”, International Journal of Engineering Research-Online A Peer Reviewed International Journal Articles Vol.3., Issue.6., 2015 (Nov.-Dec.,).
[7] P. Vekatesh, P. Pushpalatha "Implementation of aging aware reliable multiplier with kogge-stone adder", International journal of innovation research in computer and communication engineering. Articles Vol.4., Issue.10., 2016 ISSN 2320-9798.
[8] G. Vishnu Chakra Rao, P. Pushpalatha " An optimized universal shift register using pulsed latches" International journal for technological research in engineering. Articles Vol.4., Issue.4., 2016 ISSN No. (Online) : 2347-4718 Peer Reviewed (IF = 4.62)
[9] B. Spandana, P. Pushpalatha "Design of Fixed-Point DLMS adaptive filter using different adders" IJSETR Articles Vol.5., Issue.48., 2016 ISSN No. 2319-8885 Peer Reviewed (IF = 5.762)
[10] V. Vijayalakshmi, P. Pushpalatha "Optimized pattern generation using MSIC with bit swapping LFSR based on BIST schemes" IJSETR Articles Vol.5., Issue.50., 2016 ISSN No. 2319-8885 Peer Reviewed (IF = 5.762)
[11] P. Pushpalatha, P. Srilakshmi "Performance analysis of floating point arithmetic" IJARTET Articles Vol.4., Issue.16., 2017
ISSN No. (Online) : 2394-3785 Peer Reviewed (IF = 5.338)
[12] P. Pushpalatha, I. Sai Satish " Multi fault detection and correction in fault tolerance parallel FFTs using bch code" IJRASET Articles Vol.5., Issue.11., 2017 ISSN No. 2321-9653 UGC approved (IF = 6.887)
[13] P. Pushpalatha, K. Ganesh " Performance efficient MDC based pipelined FFT processor for MIMO-OFDM" IJAERD Articles Vol.4., Issue.10., 2017 ISSN No. (Online) : 2348-4470 UGC approved (IF = 4.72)
[14] P. Pushpalatha, SK. Jabida " Detect the permanent faults in FIFO of NOC routers using single address" JETIR Articles Vol.5., Issue.6., 2018 ISSN No. 2349-5162 UGC approved (IF = 5.87)
[15] P. Pushpalatha, M. Naimisha " A New method for design and analysis of anti aliasing filter using anti – derivative approach for static non-linearities" JETIR Articles Vol.6., Issue.6., 2019 ISSN No. 2349-5162 UGC approved (IF = 5.87)
[16] P. Pushpalatha, G. Taruna Kumari " Utilization of low power linear phase FIR filter for reconfigurable applications" JETIR Articles Vol.6., Issue.6., 2019 ISSN No. 2349-5162 UGC approved (IF = 5.87)
[17] P. Pushpalatha, G. Jyothsna " Performance analysis of Gammatone filter using stochastic computations" JETIR Articles Vol.6., Issue.6., 2019 ISSN No. 2349-5162 UGC approved (IF = 5.87)
[18] R. Sushma, P. Pushpalatha " Design of high speed low power FIR filter by using systolic architecture" IJATIR Articles Vol.11., Issue.6., 2019 ISSN No. 2348-2370 Peer Reviewed (IF = 4.106)
[19] P. Pushpalatha, Y. Bharat Kumar " High speed parallel LFSR architectures based on improved state space transformations with efficient and power optimized pattern generator for high speed applications" IJREAM Articles Vol.6., Issue.7., 2020 ISSN No. 2454-9150
UGC approved (IF = 6.466)
[20] P. Pushpalatha, M. Sai vamsi kamal reddy " Design and implementation of area, power and speed efficient FIR filters based on Reversible tap delay and accumulate block optimization" IJREAM Articles Vol.6., Issue.9., 2020 ISSN No. 2454-9150 UGC approved (IF = 6.466)
[21] P. Pushpalatha, K. Harshavardhan " Error detection and correction using decimal matrix algorithm" IRJET Articles Vol.8., Issue.11., 2021 ISSN No. 2395-0072 UGC approved (IF = 6.466)
[22] M. Anantha Lakshmi, P. Pushpalatha "Design and implementation of radix8 booth encoding multiplier for low area and high speed applications" IJRASET Articles Vol.9., Issue.12., 2021ISSN No. 2321-9653 UGC approved (IF = 7.429)
[23] P. Pushpalatha, G. Lavanya " An enhanced image segmentation from 3D to 2D by using modified neural networks" IJRASET Articles Vol.9., Issue.12., 2021 ISSN No. 2321-9653 UGC approved (IF = 7.538)
[24] P. Pushpalatha, K. Manoj Kumar " Implementation of haze removal using HUE-correction based on fuzzy intensification operation JORM ISSN No. 0022-3301 UGC approved (IF = 6.466)
[25] P. Pushpalatha, K. Babulu " DESIGN AND IMPLEMENTATION OF SYSTOLIC ARCHITECTURE BASED FIR FILTER" Journal on Digital Signal Processing, Vol. 10 lssue No. 1l January - June 2022 i-manager’s Journal
[26] P. Pushpalatha, K. Babulu " Low Area High-speed Hardware Implementation of Fast FIR Algorithm for Intelligent Signal Processing application in Complex industrial systems" Journal of Signal Processing Systems SCI


Workshops/Courses Attended:1) Workshop on “Outcome Based Engineering Education” held on 05th Feb, 2013 at UCEK, JNTUK, Kakinada.
2) Workshop on “Advanced VLSI Technology (NWAVLSIT 2013) ” organized by Department of ECE, UCEK, JNTUK, Kakinada during 26th -27th April, 2013.
3) Workshop on “Communications, Signals, Image Processing (COSIP-2013)” during 28TH – 29TH June, 2013 at University College of Engineering, Vizianagaram.
4) Workshop on “Orientation programme for new faculty” organized by Directorate in association with INDO US collaboration for Engineering Education (IUCEE) during 13th-14th July, 2013.
5) Workshop on “Turnitin – An Anti Plagiarism software” on 24th January, 2014 at JNTUK.
6) Workshop on “VLSI & EDA Tools (VLSI-2014)” during 6th – 7th February, 2014 at University college of Engineering, Vizianagaram.
7) Workshop on “Teaching Communication Skills” Organized by the Directorate of Faculty Development, JNTUK on 1st March 2014 in association with Global Minds Consultancy Hyderabad.
8) Workshop on “Advanced Microcontrollers with Arduino (NW-AMC 2015)” held on 23rd and 24th July 2015 at JNTUK, Kakinada.
9) Workshop on “Management Capacity Enhancement Programme for Administrators” during 5th – 9th October, 2015 at IIM Lucknow, Noida Campus.
10) Workshop on “Building Embedded Systems with ARM Cortex –M MCUs” on 18th and 19th December 2015 at JNTUK, Kakinada.
11) Workshop on “Improving the Presentation Skills in Teaching” at JNTUK Kakinada on 17th November, 2016.

SHORT TERM COURSES ATTENDED:
1) Short term course on “Advances in VLSI Signal Processing” offered by IIT Kharagpur on 3rd July 2013.
2) Faculty Development Programme on “VLSI Design” at VNRVJIET, Hyderabad during 20th May – 1st June 2013.
3) Refresher course on “Intellectual Property Rights and Patents” during 16th – 30th May, 2016 at JNTUK, Kakinada
4) Refresher course on “Research methodologies” during 1st – 15th May, 2016 at JNTUK, Kakinada.
5) Short term course on “Cognitive Radio and Wireless Communication-Teory , Practice and Security” during 1st-10th September,2016 at IIT Kanpur.
6) Short term course on “Orientation Programme” held during 4th to 31st December, 2014 at UGC-Academic Staff College, MANUU, Hyderabad.
7) Two-week refresher course on "Intellectual Property Rights and Patents" held at JNTUK during 16th – 30th May 2016.
8) One week national workshop on "Recent Advancements in VLSI Technology and Design using EDA Tools" held at UCEK,JNTUK during 20th – 24th July 2016.
9) GIAN course on Cognitive Radio and Wireless Communications-Theory, Practice and Security held at IIT KANPUR during 1st – 10th Sep 2016.
10) One week Inter Disciplinary Short Term Course on Smart Electric Power Grid with Emphasis on Embedded Systems and Cyber Security held at JNTUK during 21st – 25th Feb 2017.
11) One week Faculty development Programme on Internet of Things (IoT) Applications held at UCEK, JNTUK during 22nd – 27th Jan 2018.
12) One Week Faculty Development Programme on Improving Teaching Skills in Electonic Devices and Circuits held at JNTUK during 27th – 31st Mar 2018.
13) One week short term training programme on CNC and Robotics Programming in Manufacturing Industries held at UCEK, JNTUK in collaboration with CET, APSSDC during 2nd – 7th July 2018.
14) One week training program on Software Project Development through Python held at UCEK, JNTUK during 6th – 11th July 2018.
15) One week faculty development programme on Recent Trends in Communication Engineering held at UCEK, JNTUK Sponsored by AICTE during 4th – 9th Feb 2019.
16) One week faculty development programme on Advanced Vibration Analysis and Its Practical Applications held at UCEK, JNTUK during 11th – 16th Feb 2019.
17) Three week summer course on Research Methodologies held at JNTUK during 1st – 17th May 2019.
18) Two week faculty development programme on Noise, Acoustics, Vibration Control and Measurement in various engineering applications with hands on sessions held at UCEK, JNTUK Sponsored by AICTE during 4th – 15th June 2019.
19) One week FDP on Advancements in Manufacturing and Welding held at UCEK, JNTUK in collaboration with CET, APSSDC during 17th – 22nd June 2019.
20) One week online faculty development programme on recent advances in communications & signal processing held at UCEV, JNTUK during 24th – 29th Aug 2020.
21) Twelve week NPTEL online Certification course on Digital Electronic Circuits held at SWAYAM NPTEL during 27th Jan 2020 to 14th Apr 2020.
22) Twelve week NPTEL online Certification course on Digital System Design (Topper for this subject) held at SWAYAM NPTEL during 27th Jan 2021 to 14th Apr 2021.
23) One week online short term training programme on Advanced Vibrations – Various Engineering Applications with Hands on Sessions held at UCEK, JNTUK Sponsored by AICTE during 08th – 13th Feb 2021.
24) Verilog HDL : VLSI Hardware Design Comprehensive Masterclass online course held at UDEMY on 17 Mar 2021.
25) Two week online faculty development programme on Recent Advances in Materials and Challenges in Manufacturing Techniques held at UCEK, JNTUK during 22nd – 03rd Apr 2021.

Workshops/Conferences Organized:1) Conducted One week National Workshop on “Recent Advancement in VLSI Technology and Design Using EDA Tools (VLSITP-2016)” during 20th – 24th of July, 2016, at University College of Engineering Kakinada, JNTUK, Kakinada.
2) Conducted Two day Workshop on “Autonomous Robotics & Embedded Systems” during 22nd and 23rd of August, 2015, at University College of Engineering Kakinada, JNTUK, Kakinada.
3) Conducted National level technical symposium during Feb 28 & March 1, 2015 at University College of Engineering Kakinada, JNTUK, Kakinada.
4) Conducted Two day National Workshop on “Advanced VLSI Technology (VLSIT-13)” during 26th – 27th of April, 2013, at University College of Engineering Kakinada, JNTUK, Kakinada.
5) Conducted One week Faculty Development Program on "Teacher Orientation Program for 21st Century Education in tune with National Educational Policy 2020 (TOP NEP 2020)" during 01 August to 06 August 2022 at JNTUK, Kakinada.
Book Chapters/Books Authored:NIL
Conferences:[1] P.Pushpalatha , J.Lakshmana Kumar , P.V.Muralidhar, “Power reduction technique for content addressable memory circuit”, International Conference on Ameliorations in Communications & Power Engineering(ICACP-12).
[2] M.Suneela, P.Pushpalatha, “ Design of Area Efficient Low Power CMOS Fulladder Using 32NM Technology”, International conference on Electrical,Electronics and Computer Engineering(ICEECE – 2013).
[3] Arunadevi Jawahar, P.Pushpalatha, “Implementation of High-Order FIR Digital Filtering For Software Defined Radio Receivers”, International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES-2016).
[4] Vaka Saranya, P.Pushpalatha, “Implementation of Multiplier Architecture Using Efficient Carry Select adders for synthesizing FIR filters”, International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES-2016).
[5] Pinapothu Srilakshmi, P.Pushpalatha “Implementation of Fused Floating Four Term Dot Product Unit using Modified Booth Algorithm”, International Conference on Power,Control,Signals & Instrumentation Engineering (ICPCSI-2017).
[6] K Ganesh, P.Pushpalatha “Implementation of a High-Speed Pipelined FFT Processor using Dadda Multipliers to Process Two Independent Data Streams”, International Conference on Reliability,Infocom Technologies and Optimization(ICRITO-2017).
[7] Sai Satish Inala, P.Pushpalatha “Relative Performance of Multipliers: A fault Tolerance Perspective for Parallel FFTs”, International Conference on Reliability,Infocom Technologies and Optimization(ICRITO-2017).
[8] Sushma Revulagadda, P.Pushpalatha “Performance Analysis of Digital Based FIR Using Efficient Contraction Method”, International Conference on Signal Processing, Communication & Electronics Enginnering” (ICSPCEE-2019).
[9] G Taruna Kumari, P.Pushpalatha “Performance Analysis Of Low Power Linear Phase FIR Filter by Reconfigurable Applications and Cascaded Form”, International Conference on Innovations in Electronics and Communication Engineering (ICIECE-2019).
[10] M Naimisha, P.Pushpalatha “Anti Aliasing Filter Design For Multi Non-Linearity Systems”, International Conference on Nano Technology, Renewable Materials Engineering and Environmental Engineering (ICNRMEEE-2019).
[11] Y Bharath Kumar, P.Pushpalatha “High Speed Parallel LFSR Architecture Based on Improved State Space Transformations With Efficient and Power Optimized Pattern Generator For High Speed Applications”, International Conference on Multi Disciplinary Perspective Engineering and Technology (ICMPET-2020).
[12] P.Pushpalatha, M Sai Vamshi Kamal Reddy “Design and Implementation Of Efficient FIR Filters Using Reversible Logic Gates in TDA Block Optimized FIR Filter”, International Conference on Recent Innovations in Research and Developments (ICRIRD-2020).
[13] P.Pushpalatha, K Babulu "Design Of Digital FIR Filter With Systolic Architecture Using Reversible Logic Gates", International Conference on Recent Advances in Electrical,Electronics,Ubiquitous Communication and Computational Intelligence (RAEEUCCI-2022).

National Conferences:
1. K.Aruna, P.Pushpalatha, “ VLSI Implementation and Optimization of CAM with a gated power ML sense amplifier”, national conference on VLSI Design, Signal Processing, Image Processing, Communications & Embedded Systems(VSPICE2K15).
2. Shaik Jabida, P.Pushpalatha “The Improved Efficiency Of Permanent Faults In Fifo Of Noc Router Using Single Order Address With Ring Counter”, National Conference on VLSI Design,Signal Processing,Image Processing, Communications & Embedded Systems” (VSPICE2K18).
3. M Sri Anantha Lakshmi, P Pushpalatha "Density and Latency Optimized Efficient Filter Design Foe Spectrum sensing", IETE National Conference on VLSI, Communication and Signal Processing (NCVCS-2021).
Session Chair/Keynote Speaker/Guest Lecture:1. Session Chair for NCVSPICE-2K15 on 6-7,November 2015 at ECE Department, UCEK, JNTUK,KAKNADA
2. Session Chair for Paper presentation ESPARX 2K13,14,15,16 at ECE Department, UCEK, JNTUK,KAKNADA
3. Guest lecture delivered on various topics like VLSI using IOT, Embedded web Technology, Facial Recognition System, Bio-Chip Technology, Power Reduction using CMOS in VLSI, and 3D power Scaling at affiliated colleges of JNTUK.
R&D Projects:Nil
Ph.D Scholars guided:Nil
PG Scholars guided :28
Memberships in Professional bodies:IETE
Positions held :Deputy Warden, Project Co-Ordinator for M.Tech(VLSI&ES)
Honors & Awards:Nil
Patents :Nil
Foreign Visits:NIL